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| Home | Photosets User Guide |
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We believe the A17, announced in Sept or Oct, will include LESS on-chip SRAM than the previous two generations of A-series chips. Due to the fact that yields are down, wafer costs are up, & most-impoprtantly, because there is little to NO SRAM Scaling benefit with TSMC's 3 nm processes. However, because it is rumored that Apple has a Known Good Die purchase agreement with TSMC, it is very difficult to know for sure. We believe the sizes of the L2 & System Level Cache (SLC) should be investigated Day One, immediately upon release. This will tell us ALL whether the A17 should be compared against the A14, A15, OR A16. See the L2 & SLC sizes in the table.
| iPhone |
CPU |
GPU |
Apple Neural Engine (ANE) |
Performance Controller Notes |
||
|---|---|---|---|---|---|---|
| |
Performance Cluster Cores |
Efficiency Cluster Cores |
||||
| 15 Pro Max 5.6 GB ? LPDDR5-6400 |
A17 3 nm (N3B) |
2 ? ?(1)- ?(2) 8 MB ? L2 (?) |
4 ? (?) |
5-core ? |
16-core ? |
- |
| 16 MB ? SLC |
||||||
| 14 Pro Max 5.6 GB LPDDR5-6400 |
A16 5 nm (N4) |
2 ?(1)- ?(2) 16 MB L2 (Everest) |
4 (Sawtooth) |
5-core |
16-core |
- |
| 24 MB SLC |
||||||
| 13 Pro Max 5.6 GB LPDDR4X-4266 |
A15 5 nm (N5P) |
2 3240(1)- 3180(2) 12 MB L2 (Avalanche) |
4 2016x4 (Blizzard) |
5-core |
16-core |
- |
| 32 MB SLC |
||||||
| 12 Pro Max 5.6 GB LPDDR4X-4266 |
A14 5 nm (N5) |
2 2998(1)- 2890(2) 8 MB L2 (Firestorm) |
4 1823x4 (Icestorm) |
4-core |
16-core |
- |
| 16 MB SLC |
||||||
| 11 Pro Max 3.6 GB LPDDR4X-4266 |
A13 7 nm (N7P) |
2 2666(1)- 2590(2) 8 MB L2 (Lightning) |
4 1728x4 (Thunder) |
4-core |
8-core |
Rock Solid, Multi-Threaded |
| 16 MB SLC |
||||||
| Xs Max 3.6 GB LPDDR4X-4266 |
A12 7nm (N7) |
2 2514(1)- 2380(2) 8 MB L2 (Vortex) |
4 1587(1)- 1538(4) (Tempest) |
4-core |
2nd-Gen 8-core (1) |
Chip Bug, 2nd-Gen Multi-Threaded |
| 8 MB SLC |
||||||
| X 2.8 GB LPDDR4x-4266 |
A11 10 nm |
2 (Monsoon) |
4 (Mistral) |
3 (1st Apple designed GPU) |
1st-Gen |
Chip Bug, 1st-Gen Multi-Threaded |
| ? MB SLC |
||||||
| 7+ 3.0 GB LPDDR4-3200 |
A10 16 nm |
2 (Hurricane) |
2 (Zephyr) |
6 (licensed IP) |
- |
Rock Solid, Single-Threaded |
| ? MB SLC |
||||||
(1) The ANE in the A12 was the first one that third-party apps could access. Also: ● With the A10, ONLY the Performance cores OR the Efficiency cores can be active at one time, but NOT both. ● With the A11 & newer A-series chips, ALL CPU cores can be active at one time. -----